Popular Hands-On Tutorials Return To 40th Design Automation Conference
EDA Companies Team Up to Provide Interactive Learning Experience
BOULDER, Colo. -March 17, 2003-The Design Automation Conference (DAC), the electronic design industry's leading event, today announced the lineup for this year's hands-on tutorials, a key element of the conference's diverse program. With an emphasis on signal and power analysis, these tutorials presented by various DAC exhibitors will be in-depth, interactive sessions that allow attendees to solve specific design challenges through guided hands-on experience using the latest tools and methodologies. DAC will be held June 2-6, 2003, at the Anaheim Convention Center, Anaheim, California.
“There's no better way to learn and understand the latest technology and tools than through actual hands-on experience,” said Ellen M. Sentovich, 40th DAC tutorial chair and research scientist at Cadence Berkeley Labs. “Because of their overwhelming popularity last year, we have decided to make the hands-on tutorials an ongoing part of our program so that attendees may have the opportunity to experience various aspects of chip design in an interactive manner.”
Interactive Learning Focuses on “Signal and Power Integrity Analysis and Methodology”
The topic for this year's hands-on tutorials will be “Signal and Power Integrity Analysis and Methodology.” The tutorials will address a wide breadth of power analysis and reduction challenges, from power distribution networks in multi-million gate ICs to signal integrity at multi-gigabit speeds. Other issues to be discussed include, gliching, coupling, noise and electromigration. Each tutorial will focus on a specific design challenge and encourage attendees to work with the tools, hands-on and in real time.
Each three-hour tutorial will be limited to the first 30 enrollees, with a cost of $50 per tutorial. Student-to-workstation ratios will be 2:1. The seven selected tutorials will take place Monday through Thursday, June 2-5, and include:
- “What Is All This Noise About Signal and Power Integrity?”
Sequence Design
- “Signal and Power Integrity Analysis and Methodology”
Cadence Design Systems, IOTA Technology, and Synplicity
- “Power and Signal Integrity Simulation of PCBs and Packages”
Sigrity
- “Ensuring Signal and Power Integrity at Nanometer Technologies”
Magma Design Automation
- “3.125 Gbps With Your Hair on Fire: Simulation-Based Signal Integrity Analysis of Digital Interconnects at Multi-Gigabit Speeds”
Xilinx and Mentor Graphics Corp.
- “Full-Chip Dynamic Power Grid Methodology from Planning to Verification”
Apache Design Solutions
- “Signal and Power Integrity Validation with In-Circuit Measurements”
NPTest
For more information on DAC's program, visit the DAC Web site at www.dac.com.
Registration
To register for DAC, as well as the hands-on tutorials, call 800-321-4573 in the U.S. or visit www.dac.com. The advance conference registration discount deadline is May 5, 2003.
About DAC
DAC is the premier forum for the electronic design industry to exchange information on products, methodologies, and processes. Attended by more than 10,000 developers, designers, researchers, managers and engineers from leading electronics companies and universities around the world, DAC includes more than 150 exhibitors and offers a robust technical program covering the electronics industry's hottest trends.
The conference is sponsored by the Association for Computing Machinery/Special Interest Group on Design Automation (ACM/SIGDA), the Institute of Electrical and Electronics Engineers/Circuits and Systems Society (IEEE/CASS) and the Electronic Design Automation Consortium (EDA Consortium). For more information, including registration, visit the DAC Web site at www.dac.com, or contact DAC management at 800-321-4573.
For more information, contact:
Julia Kelly-Echeverio
Fleishman-Hillard
Public Relations for the 40th Design Automation Conference
503-721-4256
kellyej@fleishman.com
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